| 257 | -- | 264 | Giuseppe Alia, Enrico Martinelli. A VLSI structure for::::X::::(mod::::m::::) operation |
| 265 | -- | 278 | Jef L. van Meerbergen, Jos Huisken, Paul E. R. Lippens, O. McArdle, R. Segers, Gert Goossens, J. Vanhoof, Dirk Lanneer, Francky Catthoor, Hugo De Man. An integrated automatic design system for complex DSP algorithms |
| 279 | -- | 285 | R. Schreiber. Bidiagonalization and symmetric tridiagonalization by systolic arrays |
| 287 | -- | 306 | Francky Catthoor, Dirk Lanneer, Hugo De Man. Efficient microcoded processor design for fixed rate DFT and FFT |
| 307 | -- | 320 | Oscar H. Ibarra, Tao Jiang, Jik H. Chang, Michael A. Palis. Systolic algorithms for some scheduling and graph problems |
| 321 | -- | 334 | Mary Jane Irwin, Robert Michael Owens. A case for digit serial VLSI signal processors |
| 335 | -- | 343 | V. K. Prasanna Kumar, Yu-Chen Tsai. Mapping dynamic programming onto a linear systolic array |
| 345 | -- | 365 | Teresa H. Y. Meng, Robert W. Brodersen, David G. Messerschmitt. A clock-free chip set for high-sampling rate adaptive filters |
| 367 | -- | 385 | D. Bout, Paul D. Franzon, J. Paulos, T. Miller, W. Snyder, T. Nagle, Wentai Liu. Scalable VLSI implementations for neural networks |