| 207 | -- | 223 | Liang-Fang Chao, Edwin Hsing-Mean Sha. Static scheduling for synthesis of DSP algorithms on various models |
| 225 | -- | 236 | Henry Y. H. Chuang, Ling Chen. VLSI architecture for fast 2D discrete orthonormal wavelet transform |
| 237 | -- | 260 | Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri. Area efficient computing structures for concurrent error detection in systolic arrays |
| 261 | -- | 273 | Mark J. Bentum, Martin M. Samsom, Cornelis H. Slump. A multi-ASIC real-time implementation of the two dimensional affine transform with a bilinear interpolation scheme |
| 275 | -- | 293 | Liang-Gee Chen, Yeu-Shen Jehng, Tzi-Dar Chiueh. Pipeline interleaving design for FIR, IIR, and FFT array processors |
| 295 | -- | 310 | Lothar Thiele. Resource constrained scheduling of uniform algorithms |