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    Journal: VLSI Signal Processing

    Volume 11, Issue 3

    195 -- 211Giuseppe Caire, Javier Ventura-Traveset, J. Murphy, S. Y. Kung. Parallel and pipelined VLSI implementation of a staged decoder for BCM signals
    229 -- 244Kazuhito Ito, Keshab K. Parhi. Determining the minimum iteration period of an algorithm
    245 -- 262Qutaibah M. Malluhi, Magdy A. Bayoumi, T. R. N. Rao. Tree-based special-purpose Array architectures for neural computing
    263 -- 271Dusan Caf, David J. Evans. A fast solution of banded circulant systems
    273 -- 280Chen-Yi Lee, Jer-Min Tsai. A shift register architecture for high-speed data sorting
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