| 189 | -- | 199 | Roman C. Kordasiewicz, Shahram Shirani. On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC |
| 201 | -- | 221 | Sze-Wei Lee, Soon-Chieh Lim. An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems |
| 223 | -- | 232 | Wei Han, Kwok-Wai Hon, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun. A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities |
| 233 | -- | 257 | Jun-Hee Mun, Shung Han Cho, Sangjin Hong. Flexible Controller Design and Its Application for Concurrent Execution of Buffer Centric Dataflows |
| 259 | -- | 279 | Messaoud Ahmed-Ouameur, Daniel Massicotte. Real-time DSP and FPGA Implementation of Wiener LMS Based Multipath Channel Estimation in 3G CDMA Systems |
| 281 | -- | 296 | Yi-Hsuan Lee, Cheng Chen. An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture |
| 297 | -- | 315 | Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre. A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration |