Journal: VLSI Signal Processing

Volume 47, Issue 3

189 -- 199Roman C. Kordasiewicz, Shahram Shirani. On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC
201 -- 221Sze-Wei Lee, Soon-Chieh Lim. An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems
223 -- 232Wei Han, Kwok-Wai Hon, Cheong-fat Chan, Oliver Chiu-sing Choy, Kong-Pang Pun. A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities
233 -- 257Jun-Hee Mun, Shung Han Cho, Sangjin Hong. Flexible Controller Design and Its Application for Concurrent Execution of Buffer Centric Dataflows
259 -- 279Messaoud Ahmed-Ouameur, Daniel Massicotte. Real-time DSP and FPGA Implementation of Wiener LMS Based Multipath Channel Estimation in 3G CDMA Systems
281 -- 296Yi-Hsuan Lee, Cheng Chen. An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture
297 -- 315Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre. A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration

Volume 47, Issue 2

93 -- 102Roman C. Kordasiewicz, Shahram Shirani. On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC
103 -- 115Albert M. K. Cheng, Zhubin Zhang. Improving Web Server Performance with Adaptive Proxy Caching in Soft Real-time Mobile Applications
117 -- 126H. Jeong, Y. Kim. A Systolic Architecture and Implementation of Feedback Network for Blind Source Separation
127 -- 152Andrew Kinane, Noel E. O Connor. Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse
153 -- 167Chun Xue, Zili Shao, Edwin Hsing-Mean Sha. Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping
169 -- 182Albert Mo Kim Cheng, Feng Shang. Priority-driven Coding and Transmission of Progressive JPEG Images for Real-Time Applications
183 -- 187T. Sansaloni, A. Perez-Pascual, V. Torres, Javier Valls. Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs

Volume 47, Issue 1

1 -- 2Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong. Editorial for the Special Issue on Field Programmable Technology
3 -- 14Jeffrey M. Arnold. The Architecture and Development Flow of the S5 Software Configurable Processor
15 -- 31Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda. The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer
33 -- 45José Gabriel F. Coutinho, M. P. T. Juvonen, J. L. Wang, B. L. Lo, Wayne Luk, Oskar Mencer, G. Z. Yang. Designing a Posture Analysis System with Hardware Implementation
47 -- 57Máire McLoone, Ciaran McIvor. High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function
59 -- 76Marcio Juliato, Guido Araujo, Julio López, Ricardo Dahab. A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F::2:::163::::: using Gaussian Normal Bases
77 -- 92David B. Thomas, Wayne Luk. High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices