Binod Kumar 0001, Boda Nehru, Brajesh Pandey, Jaynarayan T. Tudu. Skip-scan: A methodology for test time reduction. In 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016. pages 1-6, IEEE, 2016. [doi]
@inproceedings{0001NPT16, title = {Skip-scan: A methodology for test time reduction}, author = {Binod Kumar 0001 and Boda Nehru and Brajesh Pandey and Jaynarayan T. Tudu}, year = {2016}, doi = {10.1109/ISVDAT.2016.8064869}, url = {https://doi.org/10.1109/ISVDAT.2016.8064869}, researchr = {https://researchr.org/publication/0001NPT16}, cites = {0}, citedby = {0}, pages = {1-6}, booktitle = {20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016}, publisher = {IEEE}, isbn = {978-1-5090-1422-4}, }