FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics

Shuja Ahmad Abbasi, Zulhelmi, Abdul Rahman M. Alamoud. FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics. IEICE Electronic Express, 12(16):20150450, 2015. [doi]

Authors

Shuja Ahmad Abbasi

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Zulhelmi

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Abdul Rahman M. Alamoud

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