Shuja Ahmad Abbasi, Zulhelmi, Abdul Rahman M. Alamoud. FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics. IEICE Electronic Express, 12(16):20150450, 2015. [doi]
@article{AbbasiZA15,
title = {FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics},
author = {Shuja Ahmad Abbasi and Zulhelmi and Abdul Rahman M. Alamoud},
year = {2015},
url = {https://www.jstage.jst.go.jp/article/elex/12/16/12_12.20150450/_article},
researchr = {https://researchr.org/publication/AbbasiZA15},
cites = {0},
citedby = {0},
journal = {IEICE Electronic Express},
volume = {12},
number = {16},
pages = {20150450},
}