FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics

Shuja Ahmad Abbasi, Zulhelmi, Abdul Rahman M. Alamoud. FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics. IEICE Electronic Express, 12(16):20150450, 2015. [doi]

Abstract

Abstract is missing.