Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning

Tariq B. Ahmad, Maciej J. Ciesielski. Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014. pages 619-624, IEEE, 2014. [doi]

Authors

Tariq B. Ahmad

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Maciej J. Ciesielski

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