Tariq B. Ahmad, Maciej J. Ciesielski. Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014. pages 619-624, IEEE, 2014. [doi]
@inproceedings{AhmadC14-0,
title = {Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning},
author = {Tariq B. Ahmad and Maciej J. Ciesielski},
year = {2014},
doi = {10.1109/ISVLSI.2014.47},
url = {http://dx.doi.org/10.1109/ISVLSI.2014.47},
researchr = {https://researchr.org/publication/AhmadC14-0},
cites = {0},
citedby = {0},
pages = {619-624},
booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014},
publisher = {IEEE},
}