Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim. Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. IEEE Trans. on CAD of Integrated Circuits and Systems, 35(12):2068-2081, 2016. [doi]
@article{AhnKPK16, title = {Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling}, author = {Seyong Ahn and Minseok Kang and Marios C. Papaefthymiou and Taewhan Kim}, year = {2016}, doi = {10.1109/TCAD.2016.2543022}, url = {http://dx.doi.org/10.1109/TCAD.2016.2543022}, researchr = {https://researchr.org/publication/AhnKPK16}, cites = {0}, citedby = {0}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, volume = {35}, number = {12}, pages = {2068-2081}, }