Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim. Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. IEEE Trans. on CAD of Integrated Circuits and Systems, 35(12):2068-2081, 2016. [doi]
Abstract is missing.