Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization

Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske. Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. IEEE Trans. VLSI Syst., 27(3):573-586, 2019. [doi]

Authors

Muhammad Ali

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Mohammad A. Ahmed

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Malgorzata Chrzanowska-Jeske

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