Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization

Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske. Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. IEEE Trans. VLSI Syst., 27(3):573-586, 2019. [doi]

Abstract

Abstract is missing.