Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske. Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. IEEE Trans. VLSI Syst., 27(3):573-586, 2019. [doi]
@article{AliAC19,
title = {Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization},
author = {Muhammad Ali and Mohammad A. Ahmed and Malgorzata Chrzanowska-Jeske},
year = {2019},
doi = {10.1109/TVLSI.2018.2880322},
url = {https://doi.org/10.1109/TVLSI.2018.2880322},
researchr = {https://researchr.org/publication/AliAC19},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {27},
number = {3},
pages = {573-586},
}