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Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo. Mixed Full Adder topologies for high-performance low-power arithmetic circuits. Microelectronics Journal, 38(1):130-139, 2007. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Leakage-Delay Tradeoff in FinFET Logic Circuits: a Comparative Analysis with Bulk TechnologyMatteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi. IEEE Trans. VLSI Syst., 18(2), Feb 2010. [doi] High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus TechnologyMassimo Alioto, Gaetano Palumbo. iscas 2007: 2998-3001 [doi]
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