The following publications are possibly variants of this publication:
- Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanismAlexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes. iet-cdt, 1(3):197-206, 2007. [doi]
- DfT for the Reuse of Networks-on-Chip as Test Access MechanismAlexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes. vts 2007: 435-440 [doi]
- A structured and scalable mechanism for test access to embedded reusable coresErik Jan Marinissen, Robert G. J. Arendsen, Gerard Bos, Hans Dingemanse, Maurice Lousberg, Clemens Wouters. itc 1998: 284-293 [doi]