Early timing estimation for system-level design using FPGAs (abstract only) - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Hugo A. Andrade, Arkadeb Ghosal, Rhishikesh Limaye, Sadia Malik, Newton Petersen, Kaushik Ravindran, Trung N. Tran, Guoqiang Wang, Guang Yang. Early timing estimation for system-level design using FPGAs (abstract only). In Katherine Compton, Brad L. Hutchings, editors, Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, FPGA 2012, Monterey, California, USA, February 22-24, 2012. pages 271, ACM, 2012. [doi]

This author has not been identified. Look up 'Hugo A. Andrade' in GoogleThis author has not been identified. Look up 'Arkadeb Ghosal' in GoogleThis author has not been identified. Look up 'Rhishikesh Limaye' in GoogleThis author has not been identified. Look up 'Sadia Malik' in GoogleThis author has not been identified. Look up 'Newton Petersen' in GoogleThis author has not been identified. Look up 'Kaushik Ravindran' in GoogleThis author has not been identified. Look up 'Trung N. Tran' in GoogleThis author has not been identified. Look up 'Guoqiang Wang' in GoogleThis author has not been identified. Look up 'Guang Yang' in Google

runs on WebDSL