Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau. Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. In Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada. pages 280-285, IEEE, 2006. [doi]
@inproceedings{AndriamisainaGC06,
title = {Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems},
author = {Caaliph Andriamisaina and Bertrand Le Gal and Emmanuel Casseau},
year = {2006},
doi = {10.1109/SIPS.2006.352595},
url = {http://dx.doi.org/10.1109/SIPS.2006.352595},
tags = {optimization},
researchr = {https://researchr.org/publication/AndriamisainaGC06},
cites = {0},
citedby = {0},
pages = {280-285},
booktitle = {Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada},
publisher = {IEEE},
isbn = {1-4244-0382-0},
}