The following publications are possibly variants of this publication:
- 4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XORNazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine. vlsi 2010: 364-368 [doi]
- Two phase clocked adiabatic static CMOS logicNazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine. issoc 2009: 83-86 [doi]
- LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplierNazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine. mj, 43(4):244-249, 2012. [doi]
- Fundamental logics based on two phase clocked adiabatic static CMOS logicNazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine. icecsys 2009: 503-506 [doi]
- VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS LogicYasuhiro Takahashi, Toshikazu Sekine, Michio Yokoyama. ieicet, 90-C(10):2002-2006, 2007. [doi]
- 2PADCL: Two Phase drive Adiabatic Dynamic CMOS LogicYasuhiro Takahashi, Youhei Fukuta, Toshikazu Sekine, Michio Yokoyama. apccas 2006: 1484-1487 [doi]