Reduction of interpolants for logic synthesis

John D. Backes, Marc D. Riedel. Reduction of interpolants for logic synthesis. In 2010 International Conference on Computer-Aided Design (ICCAD 10), November 7-11, 2010, San Jose, CA, USA. pages 602-609, IEEE, 2010. [doi]

Authors

John D. Backes

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Marc D. Riedel

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