John D. Backes, Marc D. Riedel. Reduction of interpolants for logic synthesis. In 2010 International Conference on Computer-Aided Design (ICCAD 10), November 7-11, 2010, San Jose, CA, USA. pages 602-609, IEEE, 2010. [doi]
@inproceedings{BackesR10,
title = {Reduction of interpolants for logic synthesis},
author = {John D. Backes and Marc D. Riedel},
year = {2010},
doi = {10.1109/ICCAD.2010.5654209},
url = {http://dx.doi.org/10.1109/ICCAD.2010.5654209},
tags = {logic},
researchr = {https://researchr.org/publication/BackesR10},
cites = {0},
citedby = {0},
pages = {602-609},
booktitle = {2010 International Conference on Computer-Aided Design (ICCAD 10), November 7-11, 2010, San Jose, CA, USA},
publisher = {IEEE},
}