An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Seung-Jun Bae, Kwang-Il Park, Jeong-Don Ihm, Ho-Young Song, Woo Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Yoon-Sik Park, Min-Sang Park, Hong-Kyong Lee, Sam-Young Bang, Gil-Shin Moon, Seokwon Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim, Ji-Hoon Lim, Jae-Sung Kim, Sunghoon Kim, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim, Soo-In Cho. An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. J. Solid-State Circuits, 43(1):121-131, 2008. [doi]

Authors

Seung-Jun Bae

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Kwang-Il Park

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Jeong-Don Ihm

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Ho-Young Song

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Woo Jin Lee

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Hyun-Jin Kim

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Kyoung-Ho Kim

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Yoon-Sik Park

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Min-Sang Park

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Hong-Kyong Lee

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Sam-Young Bang

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Gil-Shin Moon

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Seokwon Hwang

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Young-Chul Cho

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Sang-Jun Hwang

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Dae-Hyun Kim

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Ji-Hoon Lim

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Jae-Sung Kim

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Sunghoon Kim

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Seong-Jin Jang

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Joo-Sun Choi

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Young-Hyun Jun

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Kinam Kim

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Soo-In Cho

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