Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires

Anahita Bagheri, Nasser Masoumi. Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires. Microelectronics Journal, 43(12):1038-1045, 2012. [doi]

@article{BagheriM12,
  title = {Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires},
  author = {Anahita Bagheri and Nasser Masoumi},
  year = {2012},
  doi = {10.1016/j.mejo.2012.08.003},
  url = {http://dx.doi.org/10.1016/j.mejo.2012.08.003},
  researchr = {https://researchr.org/publication/BagheriM12},
  cites = {0},
  citedby = {0},
  journal = {Microelectronics Journal},
  volume = {43},
  number = {12},
  pages = {1038-1045},
}