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A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder

Fujun Bai, Song Wang, Xuerong Jia, Yi-Xin Guo, Bing Yu, Hang Wang, Cong Lai, Qiwei Ren, Hongbin Sun 0001. A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder. IEEE Trans. VLSI Syst., 31(1):128-141, 2023. [doi]

Authors

Fujun Bai

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Song Wang

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Xuerong Jia

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Yi-Xin Guo

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Bing Yu

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Hang Wang

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Cong Lai

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Qiwei Ren

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Hongbin Sun 0001

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