Fujun Bai, Song Wang, Xuerong Jia, Yi-Xin Guo, Bing Yu, Hang Wang, Cong Lai, Qiwei Ren, Hongbin Sun 0001. A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder. IEEE Trans. VLSI Syst., 31(1):128-141, 2023. [doi]
@article{BaiWJGYWLRS23,
title = {A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder},
author = {Fujun Bai and Song Wang and Xuerong Jia and Yi-Xin Guo and Bing Yu and Hang Wang and Cong Lai and Qiwei Ren and Hongbin Sun 0001},
year = {2023},
doi = {10.1109/TVLSI.2022.3219437},
url = {https://doi.org/10.1109/TVLSI.2022.3219437},
researchr = {https://researchr.org/publication/BaiWJGYWLRS23},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {31},
number = {1},
pages = {128-141},
}