Fujun Bai, Song Wang, Xuerong Jia, Yi-Xin Guo, Bing Yu, Hang Wang, Cong Lai, Qiwei Ren, Hongbin Sun 0001. A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder. IEEE Trans. VLSI Syst., 31(1):128-141, 2023. [doi]
Abstract is missing.