Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing - researchr publication authors

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Aydin O. Balkan, Michael N. Horak, Gang Qu, Uzi Vishkin. Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing. In John W. Lockwood, Fabrizio Petrini, Ron Brightwell, Dhabaleswar K. Panda, editors, 15th Annual IEEE Symposium on High-Performance Interconnects, HOTI 2007, Stanford, CA, USA, August 22-24, 2007. pages 21-28, IEEE Computer Society, 2007. [doi]

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