Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu. Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems, 28(5):651-661, 2009. [doi]
@article{BanerjeeSB09,
title = {Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs},
author = {Pritha Banerjee and Susmita Sur-Kolay and Arijit Bishnu},
year = {2009},
doi = {10.1109/TCAD.2009.2015738},
url = {http://dx.doi.org/10.1109/TCAD.2009.2015738},
researchr = {https://researchr.org/publication/BanerjeeSB09},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {28},
number = {5},
pages = {651-661},
}