Thomas S. Barnett, Adit D. Singh, Victor P. Nelson. Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. In 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings. pages 29-38, IEEE Computer Society, 2001. [doi]
@inproceedings{BarnettSN01,
title = {Yield-Reliability Modeling for Fault Tolerant Integrated Circuits},
author = {Thomas S. Barnett and Adit D. Singh and Victor P. Nelson},
year = {2001},
url = {http://computer.org/proceedings/dft/1203/12030029abs.htm},
tags = {modeling, reliability},
researchr = {https://researchr.org/publication/BarnettSN01},
cites = {0},
citedby = {0},
pages = {29-38},
booktitle = {16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings},
publisher = {IEEE Computer Society},
isbn = {0-7695-1203-8},
}