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Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme

Subhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan Chatterjee, C. K. Sarkar. Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme. In International Symposium on Electronic System Design, ISEDs 2012, Kolkata, India, December 19-22, 2012. pages 130-134, IEEE, 2012. [doi]

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