Table of Contents

• Synthesis of Reversible Circuits Using Decision DiagramsRolf Drechsler, Robert Wille. 1-5 [doi]
• Cleaning Up: Garbage-Free Reversible Circuits by Design LanguagesMichael Kirkedal Thomsen, Holger Bock Axelsen, Robert Glück. 6-10 [doi]
• Synthesis of Toffoli Networks: Status and ChallengesGerhard W. Dueck. 11-16 [doi]
• Recent Developments on Mapping Reversible Circuits to Quantum Gate LibrariesD. Michael Miller, Zahra Sasanian. 17-22 [doi]
• A Design of 6-bit 125-MS/s SAR ADC in 0.13-µm MM/RF CMOS ProcessR. Rajendran, P. V. Ramakrishna. 23-27 [doi]
• A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed ApplicationsSagar Mukherjee, Dipankar Saha, Posiba Mostafa, Sayan Chatterjee, Chandan Kumar Sarkar. 28-32 [doi]
• 0.5 V, Low Power, 1 MHz Low Pass Filter in 0.18 µm CMOS ProcessVasantha M. H., Tonse Laxminidhi. 33-37 [doi]
• Design Space Exploration and Synthesis of CMOS Low Noise AmplifiersLaxmikandan Thangavelu, Ramakrishna P. V.. 38-42 [doi]
• FPGA Based Efficient Fast FIR Algorithm for Higher Order Digital FIR FilterJ. Selvakumar, Vidhyacharan Bhaskar, S. Narendran. 43-47 [doi]
• Effect of Finite Gain and Bandwidth of Feed-Forward Compensated OTA on Active-RC Integrators: A Case StudyRekha S., Laxminidhi T.. 48-51 [doi]
• Systolic Variable Length Architecture for Discrete Fourier Transform in Long Term EvolutionC. V. Niras, Vinu Thomas. 52-55 [doi]
• SoC Time to Market Improvement through Device Driver Reuse: An Industrial ExperienceRohit Srivastava, Nandini Mudgil, Gaurav Gupta, Hemanta Mondal. 56-61 [doi]
• Confidence Based Power Aware TestingTapas Kumar Maiti, Subhadip Kundu, Arpita Dutta, Santanu Chattopadhyay. 62-66 [doi]
• A Value Propagation Based Equivalence Checking Method for Verification of Code Motion TechniquesKunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal. 67-71 [doi]
• High Speed Generic Network Interface for Network on Chip Using Ping Pong BuffersK. Swaminathan, G. Lakshminarayanan, Seok-Bum Ko. 72-76 [doi]
• Analysis and Operation of FPGA-based Hybrid Active Power Filter for Harmonic Elimination in a Distribution SystemGayadhar Panda, Santanu Kumar Dash, Nirjharini Sahoo. 77-81 [doi]
• FPGA Implementation of Particle Filter Based Object Tracking in VideoSumeet Agrawal, Pinal Engineer, Rajbabu Velmurugan, Sachin B. Patkar. 82-86 [doi]
• Post Silicon Validation of Digital Radio InterfacesDeepak Chauhan, Sharad Kumar, Manoj Sharma. 87-91 [doi]
• Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI ArchitectureAtin Mukherjee 0001, Anindya Sundar Dhar. 92-96 [doi]
• A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM CellSanthosh Keshavarapu, Saumya Jain, Manisha Pattanaik. 97-101 [doi]
• A Modified Twin Precision Multiplier with 2D Bypassing TechniqueSyed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas. 102-106 [doi]
• Improved Design of High-Radix Signed-Digit AddersFateme Naderpour, SeokBum Ko. 107-110 [doi]
• Systolic FIR Filter Design with Various Parallel Prefix Adders in FPGA: Performance AnalysisR. Uma, Jebashini Ponnian. 111-115 [doi]
• Comparison of FFT/IFFT Designs Utilizing Different Low Power TechniquesKwen-Siong Chong, Joseph S. Chang, Idongesit E. Ebong, Yalcin Yilmaz, Pinaki Mazumder. 116-119 [doi]
• Dynamic Sharing of On-Chip Scratchpad Memory on Embedded PlatformsSandip Ghosh, Prokash Ghosh, Sourav Roy. 120-124 [doi]
• GPU-based Parallel Implementation of SAR ImagingXingxing Jin, Seok-Bum Ko. 125-129 [doi]
• Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT SchemeSubhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan Chatterjee, C. K. Sarkar. 130-134 [doi]
• CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test ApplicationsS. Sivanantham, K. Sarathkumar, Jincy P. Manuel, Partha Sharathi Mallick, J. Raja Paul Perinbam. 135-139 [doi]
• Improvements for High Performance Elliptic Curve Cryptosystem Processor over GF(2^163)K. C. Cinnati Loi, Seok-Bum Ko. 140-144 [doi]
• High Speed Hardware for March C¯Mousumi Saha, Souvik Das, Biplab K. Sikdar. 145-147 [doi]
• Bridging Validation and Automatic Test Equipment (ATE) EnvironmentAshish Gupta, Gaurav Verma. 148-150 [doi]
• A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR GateVikas Mahor, Akanksha Chouhan, Manisha Pattanaik. 151-153 [doi]
• Design of Hardware for Deterministic Nagel-Schreckenberg Traffic ModelRaju Hazari, Kamalika Bhattacharjee, Sukanta Das. 154-156 [doi]
• Design, Development and Testing of a DSP Based Dynamic Voltage RestorerAnirban De, S. Kumari, V. K. Khare, S. S. Pal, Anindya Sadhukhan, V. K. Meshram, S. K. Thakur, S. Saha. 157-161 [doi]
• Identifying Faulty TSVs in 3D Stacked IC during Pre-bond TestingSurajit Kumar Roy, Sobitri Chatterjee, Chandan Giri. 162-166 [doi]
• Finding Critical Components in Embedded Control Systems Sensitive to Quality-FaultsVishal Shrivastav, Satya Gautam Vadlamudi, P. P. Chakrabarti, Dipankar Das 0002, Purnendu Sinha. 167-171 [doi]
• Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm OptimizationPradip Kumar Sahu, Ashish Sharma, Santanu Chattopadhyay. 172-176 [doi]
• e-SURAKSHAK: A Cyber-Physical Healthcare System with Service Oriented ArchitectureI. Hiteshwar Rao, Nafisa Ali Amir, Haresh Dagale, Joy Kuri. 177-182 [doi]
• From Requirements and Scenarios to ESL Design in SystemCHoang M. Le, Daniel Große, Rolf Drechsler. 183-187 [doi]
• Multiple Dilution Sample Preparation Using Digital Microfluidic BiochipsSukanta Bhattacharjee, Ansuman Banerjee, Bhargab B. Bhattacharya. 188-192 [doi]
• Design of a Static Current Simulator Using Device Matrix ApproachDeepak Bharti, Abhijit R. Asati. 193-197 [doi]
• Analysis of Contact Resistance Effect on Performance of Organic Thin Film TransistorsBrijesh Kumar, Brajesh Kumar Kaushik, Yuvraj Singh Negi. 198-202 [doi]
• Low-Cost Dilution Engine for Sample Preparation in Digital Microfluidic BiochipsSudip Roy 0001, Bhargab B. Bhattacharya, Sarmishtha Ghoshal, Krishnendu Chakrabarty. 203-207 [doi]
• Design of 4-Bit Array Multiplier Using Multi-wall Carbon Nanotube InterconnectsDebaprasad Das, Sourav Das, Hafizur Rahaman. 208-212 [doi]
• The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design IssuesNaushad Alam, Bulusu Anand, Sudeb Dasgupta. 213-215 [doi]
• A Test Design for Quick Determination of Incoherency in Chip Multiprocessors' Cache Realizing MOESI ProtocolMamata Dalui, Biplab K. Sikdar. 216-220 [doi]
• SD2D: A Novel Routing Architecture for Network-on-ChipPrasun Ghosal, Tuhin Subhra Das. 221-225 [doi]
• Particle Swarm Optimization Based Circuit Synthesis of Reversible LogicKamalika Datta, Indranil Sengupta 0001, Hafizur Rahaman. 226-230 [doi]
• Fractional Interpretation of Anomalous Diffusion and Semiconductor EquationsRohith G., Ajayan K. K.. 231-235 [doi]
• Efficient and Compact Electrical Modeling of Multi Walled Carbon Nanotube InterconnectsManodipan Sahoo, Prasun Ghosal, Hafizur Rahaman. 236-240 [doi]
• Design of Fault Tolerant Reversible Arithmetic Logic Unit in QCABibhash Sen, Manojit Dutta, Debajyoty Banik, Dipak K. Singh, Biplab K. Sikdar. 241-245 [doi]
• Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm OptimizationPapia Manna, Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya. 246-250 [doi]
• Electrooculogram Based Online Control Signal Generation for WheelchairAnwesha Banerjee, Shounak Datta, Pratyusha Das, Amit Konar, D. N. Tibarewala, Ramadoss Janarthanan. 251-255 [doi]
• System on Biochips: A New Design for Integration of Multiple DMFBsPranab Roy, Moudud Sohid, Sudipta Chakraborty, Hafizur Rahaman, Parthasarathi Dasgupta. 256-260 [doi]
• Analysis of Top and Bottom Contact Organic Transistor Performance for Different Technology NodesPoornima Mittal, Yuvraj Singh Negi, R. K. Singh. 261-263 [doi]
• Improvement in Target Detectability Using Spread Spectrum Radar in Dispersive Channel ConditionSoumyasree Bera, Arun Kumar Singh, Samarendra Nath Sur, Debasish Bhaskar, Rabindranath Bera. 264-266 [doi]
• Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed FrameworkR. Mukherjee, P. Ghosh, N. Sravan Kumar, P. Dasgupta, A. Pal. 267-271 [doi]
• Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS AddersShashikant Sharma, Manisha Pattanaik, Balwinder Raj. 272-275 [doi]
• An Improved Soft Switching DC-DC Converter for Low Power PV ApplicationsSatarupa Bal, Anup Anurag, B. Chitti Babu. 276-280 [doi]
• Modeling, Analysis and Design of Synchronous Buck Converter Using State Space Averaging Technique for PV Energy SystemGunda Suman, B. V. S. Pavan Kumar, M. Sagar Kumar, B. Chitti Babu, K. R. Subhashini. 281-285 [doi]
• Enhancement of Medical Ultrasound Images Using Multiscale Discrete Shearlet Transform Based ThresholdingDeep Gupta, R. S. Anand, Barjeev Tyagi. 286-290 [doi]
• Performance Analysis of Offloading IPsec Processing to Hardware Based AcceleratorsHemant Agrawal, Yashpal Dutta, Sandeep Malik. 291-294 [doi]
• A Closed-Loop Control Strategy for Glucose Control in Artificial Pancreas SystemsJ. Galadanci, R. A. Shafik, J. Mathew, A. Acharyya, D. K. Pradhan. 295-299 [doi]
• A Delaunay Triangulation Preprocessing Based Fuzzy-Encroachment Graph Clustering for Large Scale GIS DataParthajit Roy, J. K. Mandal. 300-305 [doi]
• Fractal Image Compression Using Fast Context Independent HV Partitioning SchemeUtpal Nandi, J. K. Mandal. 306-308 [doi]
• Energy Aware Spectrum Decision Framework for Cognitive Radio NetworksVishram Mishra, Chiew Tong Lau, Syin Chan, Ashish Kumar. 309-313 [doi]
• Policy Based ACL Configuration Synthesis in Enterprise Networks: A Formal ApproachSoumya Maity, Padmalochan Bera, S. K. Ghosh. 314-318 [doi]