Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures

Hareesh-Reddy Basireddy, Karthikeya Challa, Tooraj Nikoubin. Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures. IEEE Trans. VLSI Syst., 27(5):1138-1147, 2019. [doi]

Abstract

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