Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits

Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia. Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits. In First Great Lakes Symposium on VLSI, 1991, Kalamazoo, MI, USA, March 1-2, 1991. pages 340-341, IEEE, 1991. [doi]

@inproceedings{BasuWBM91,
  title = {Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits},
  author = {Anupam Basu and Thomas Charles Wilson and Dilip K. Banerji and Jayanti C. Majithia},
  year = {1991},
  doi = {10.1109/GLSV.1991.143994},
  url = {http://dx.doi.org/10.1109/GLSV.1991.143994},
  researchr = {https://researchr.org/publication/BasuWBM91},
  cites = {0},
  citedby = {0},
  pages = {340-341},
  booktitle = {First Great Lakes Symposium on VLSI, 1991, Kalamazoo, MI, USA, March 1-2, 1991},
  publisher = {IEEE},
  isbn = {0-8186-2170-2},
}