Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits

Anupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia. Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits. In First Great Lakes Symposium on VLSI, 1991, Kalamazoo, MI, USA, March 1-2, 1991. pages 340-341, IEEE, 1991. [doi]

Abstract

Abstract is missing.