The following publications are possibly variants of this publication:
- A 600-Mb/s encoder and decoder for low-density parity-check convolutional codesTyler L. Brandon, John C. Koob, Leendert van den Berg, Zhengang Chen, Amirhossein Alimohammad, Ramkrishna Swamy, Jason Klaus, Stephen Bates, Vincent C. Gaudet, Bruce F. Cockburn, Duncan G. Elliott. iscas 2008: 3090-3093 [doi]
- A Low-Cost Serial Decoder Architecture for Low-Density Parity-Check Convolutional CodesStephen Bates, Zhengang Chen, Logan Gunthorpe, Ali Emre Pusane, Kamil Sh. Zigangirov, Daniel J. Costello Jr.. tcas, 55-I(7):1967-1976, 2008. [doi]
- A memory-based architecture for FPGA implementations of low-density parity-check convolutional decodersStephen Bates, Gary Block. iscas 2005: 336-339 [doi]
- Design and Test of a 175-Mb/s, Rate-1/2 (128, 3, 6) Low-Density Parity-Check Convolutional Code Encoder and DecoderRamkrishna Swamy, Stephen Bates, Tyler L. Brandon, Bruce F. Cockburn, Duncan G. Elliott, John C. Koob, Zhengang Chen. jssc, 42(10):2245-2256, 2007. [doi]