A Design of BNN Accelerator using Gate-level Pipelined Self-Synchronous Circuit - researchr publication authors

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Amartuvshin Bayasgalan, Makoto Ikeda. A Design of BNN Accelerator using Gate-level Pipelined Self-Synchronous Circuit. In International Conference on IC Design and Technology, ICICDT 2023, Tokyo, Japan, September 25-28, 2023. pages 20-24, IEEE, 2023. [doi]

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