A Design of BNN Accelerator using Gate-level Pipelined Self-Synchronous Circuit

Amartuvshin Bayasgalan, Makoto Ikeda. A Design of BNN Accelerator using Gate-level Pipelined Self-Synchronous Circuit. In International Conference on IC Design and Technology, ICICDT 2023, Tokyo, Japan, September 25-28, 2023. pages 20-24, IEEE, 2023. [doi]

@inproceedings{BayasgalanI23,
  title = {A Design of BNN Accelerator using Gate-level Pipelined Self-Synchronous Circuit},
  author = {Amartuvshin Bayasgalan and Makoto Ikeda},
  year = {2023},
  doi = {10.1109/ICICDT59917.2023.10332413},
  url = {https://doi.org/10.1109/ICICDT59917.2023.10332413},
  researchr = {https://researchr.org/publication/BayasgalanI23},
  cites = {0},
  citedby = {0},
  pages = {20-24},
  booktitle = {International Conference on IC Design and Technology, ICICDT 2023, Tokyo, Japan, September 25-28, 2023},
  publisher = {IEEE},
  isbn = {979-8-3503-1931-6},
}