Alp Arslan Bayrakci, Alper Demir, Serdar Tasiran. Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(9):1328-1341, 2010. [doi]
@article{BayrakciDT10,
title = {Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation},
author = {Alp Arslan Bayrakci and Alper Demir and Serdar Tasiran},
year = {2010},
doi = {10.1109/TCAD.2010.2049042},
url = {http://dx.doi.org/10.1109/TCAD.2010.2049042},
researchr = {https://researchr.org/publication/BayrakciDT10},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {29},
number = {9},
pages = {1328-1341},
}