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Alp Arslan Bayrakci, Alper Demir, Serdar Tasiran. Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(9):1328-1341, 2010. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Fast and accurate statistical timing analysis of digital circuits for timing yield estimation based on transistor level simulations (Transistör düzeyi simülasyonlara dayanan zamanlama verimi tahmini için sayısal devrelerin hızlı ve doğru istatiksel zamanlama analizi)Alp Arslan Bayrakci. PhD thesis, Koç University, Turkey, 2010. [doi]
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