Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation

Alp Arslan Bayrakci, Alper Demir, Serdar Tasiran. Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(9):1328-1341, 2010. [doi]

Abstract

Abstract is missing.