Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality - researchr publication

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Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press. Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany. pages 56-61, IEEE Computer Society, 2005. [doi]

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