R. Berthelon, François Andrieu, P. Perreau, E. Baylac, A. Pofelski, Emmanuel Josse, D. Dutartre, A. Claverie, Michel Haond. Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration. In 46th European Solid-State Device Research Conference, ESSDERC 2016, Lausanne, Switzerland, September 12-15, 2016. pages 127-130, IEEE, 2016. [doi]
@inproceedings{BerthelonAPBPJD16,
title = {Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration},
author = {R. Berthelon and François Andrieu and P. Perreau and E. Baylac and A. Pofelski and Emmanuel Josse and D. Dutartre and A. Claverie and Michel Haond},
year = {2016},
doi = {10.1109/ESSDERC.2016.7599604},
url = {http://dx.doi.org/10.1109/ESSDERC.2016.7599604},
researchr = {https://researchr.org/publication/BerthelonAPBPJD16},
cites = {0},
citedby = {0},
pages = {127-130},
booktitle = {46th European Solid-State Device Research Conference, ESSDERC 2016, Lausanne, Switzerland, September 12-15, 2016},
publisher = {IEEE},
isbn = {978-1-5090-2969-3},
}