Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs

Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck. Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems, 36(4):699-703, 2017. [doi]

Authors

Endri Bezati

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Simone Casale Brunet

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Marco Mattavelli

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Jörn W. Janneck

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