Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck. Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems, 36(4):699-703, 2017. [doi]
@article{BezatiBMJ17,
title = {Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs},
author = {Endri Bezati and Simone Casale Brunet and Marco Mattavelli and Jörn W. Janneck},
year = {2017},
doi = {10.1109/TCAD.2016.2597215},
url = {http://dx.doi.org/10.1109/TCAD.2016.2597215},
researchr = {https://researchr.org/publication/BezatiBMJ17},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {36},
number = {4},
pages = {699-703},
}