A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes

Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi. A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. In ASP-DAC. pages 367-372, 1998.

@inproceedings{BinhIT98,
  title = {A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes},
  author = {Nguyen-Ngoc Bình and Masaharu Imai and Yoshinori Takeuchi},
  year = {1998},
  tags = {constraints, design},
  researchr = {https://researchr.org/publication/BinhIT98},
  cites = {0},
  citedby = {0},
  pages = {367-372},
  booktitle = {ASP-DAC},
}