A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes

Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi. A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. In ASP-DAC. pages 367-372, 1998.

Abstract

Abstract is missing.