Sequential logic path delay test generation by symbolic analysis

Soumitra Bose, Vishwani D. Agrawal. Sequential logic path delay test generation by symbolic analysis. In 4th Asian Test Symposium (ATS 95), November 23-24, 1995. Bangalore, India. pages 353, IEEE Computer Society, 1995. [doi]

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.