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Soumitra Bose, Vishwani D. Agrawal. Sequential logic path delay test generation by symbolic analysis. In 4th Asian Test Symposium (ATS 95), November 23-24, 1995. Bangalore, India. pages 353, IEEE Computer Society, 1995. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Deriving Logic Systems for Path Delay Test GenerationSoumitra Bose, Prathima Agrawal, Vishwani D. Agrawal. TC, 47(8):829-846, 1998. Delay Fault Models and Test Generation for Random Logic Sequential CircuitsTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell. dac 1992: 165-172 [doi]
The following publications are possibly variants of this publication: